1. Field of the Invention
The invention relates generally to the configuration and manufacturing process of the semiconductor power devices. More particularly, this invention relates to an improved configuration for manufacturing an electrostatic discharge (ESD) protection circuit integrated with a semiconductor power device with reduced number of masks such that the semiconductor power device can be manufactured with simplified process, lower costs, improved production yield, and higher performance reliability.
2. Description of the Prior Art
Conventional layout for manufacturing semiconductor power devices with protection circuits against electrostatic discharges (ESD) still has a limitation. The conventional power MOSFET devices with ESD protection circuit generally have a layout and layer structures that requires application of seven masks in the typical manufacturing processes. These seven masks include a trench mask, an ESD mask, a body mask, a source mask, a contact mask, a metal mask and a passivation mask. With the seven masks required in the manufacturing processes, the processing steps are more complicated and time consuming. Additional manufacturing with more mask requirements further generates the likelihood of processing abnormalities and product defects thus degrade the performance. Finally but not least, the production costs are significantly increased not only due to the more complicated processes and manufacturing time required, but also due to the lower yields as the result of requiring more masks when the semiconductor power device is implemented with the conventional layout and layer structures.
Referring to FIGS. 1A and 1B for a cross sectional view and a top view of a conventional semiconductor power device such as a MOSFET device provided with ESD protection circuit. More specifically, the manufacturing processes and the layout with conventional layer structures as shown require a body mask to form the guard rings in the termination area. Furthermore, a passivation mask is required to open contact windows through the passivation layer for package connection, where the passivation layer is required to cover the die edge and scribe line.
Therefore, it is necessary to provide alternate layout for the ESD circuits on the semiconductor power device not limited by the conventional layout and layer structures without affecting the ESD protection ratings. It is also desirable that the new layout can reduce the mask requirements thus simplify the processing steps to achieve cost savings, improved yield and better performance and lifetime reliability of the semiconductor power devices.